The present invention is generally directed to a protection of integrated circuits (ICs) against electrostatic discharge (ESD). In particular, the present invention is directed to a device and method for protecting ICs against ESD using an isolated NMOS transistor.
Integrated circuit (IC) chips are made from semiconductor materials such as silicon and insulating materials such as silicon dioxide. Static charges may build up on exposed terminals (e.g., pins) of an IC chip. These static charges remain on those terminals of the IC chip until either bleed off to ground or are neutralized by a discharge. ESD is a sudden and momentary electric current that flows between two points with opposite charges. Internal circuitry of IC chips may suffer damage due to ESD. In order to prevent the damage, exposed terminals of the IC chips may be provided with a protection circuit to conduct ESD current when there is static charge build up.
One type of transistor for an IC chip are metal-oxide-semiconductor field-effect (MOS FET or MOS) transistors. MOS transistors operate by forming a channel between two doped regions (e.g., source and drain) and conducting electrical current via the channel by a certain electrical carrier (e.g., n type (electrons) or p type (holes)). Based on the types of the carrier, a MOS transistor may be termed as an NMOSFET (e.g., a n type MOS) or a PMOSFET (e.g., a p type MOS) (also commonly referred to as NMOS, PMOS). The channel of a MOS transistor is controlled by a gate, which normally uses a silicon oxide film (also referred to as the gate oxide film) as an insulating film to separate the gate and the channel. Because MOS transistors use only one type of electrical carrier, they may be termed as unipolar transistors. In contrast to MOS transistors are bipolar transistors, which operate by conducting electrical current using both types of electrical carriers (e.g., electrons and holes).
In one type of MOS transistors, the two doped regions are formed directly on a substrate with an opposite electrical carrier (e.g., p type regions on a n type substrate or n type regions on a p type substrate). For example, an NMOS transistor may be manufactured by forming two n type doped regions on a p type substrate and a gate of silicon oxide film over the channel between the two n typed doped regions. This type of MOS transistor typically is used with a low operational voltage (e.g., ±2.5 volts, or ±1.5 volts).
In another type of MOS transistor, called “isolated” NMOS or PMOS transistors, the two doped regions may be formed on a backgate layer, which is isolated from the substrate layer by an isolation layer. The backgate layer and the substrate have same type of electrical carrier and the isolation layer has an opposite electrical carrier. Isolated NMOS or PMOS transistors can have a relatively wider range of operational voltage (e.g., ±12 volts or ±15 volts).
FIG. 1 shows a cross section of a conventional isolated NMOS transistor 100. In the isolated NMOS transistor 100, an n type isolation region 104 isolates the p type backgate 106 from the p type substrate 102. Two n type doped regions 108 and 110 form the drain and source of the NMOS transistor. A gate 112 is formed between the drain 108 and the source 110. The backgate 106 contains a doped region 114 to connect the backgate 106 to a terminal. A doped region 116 of the substrate 102 may connect the substrate 102 to another terminal (e.g., ground). In a symmetrical isolated NMOS transistor, the drain 108 and the source 110 are interchangeable.
Although the isolated NMOS transistor 100 is designed as an MOS transistor, in effect, three parasitic npn bipolar transistors labeled T1, T2 and T3 are formed. These bipolar transistors operate by involving both negative and positive electrical carriers (e.g., electrons and holes). The n type isolation region 104 forms the collectors of both T1 and T2, while the p type backgate 106 forms the bases of both T1 and T2. The drain 108 forms the emitter of T1, while the source 110 forms the emitter of T2. T3 is formed by the drain 108 as the collector, the backgate 106 as the base and the source 110 as the emitter.
During manufacturing, assembly, installation and/or operation of an IC chip, static charges may accumulate on external terminals (e.g., pins) of the IC chip. The isolated NMOS transistor 100 may be used to connect the IC to some external circuits (e.g., power supplies, signals). If there is static charge build up on those external terminals, different regions of the isolated NMOS transistor 100 may reach different potential levels. The different potential levels between different regions may create electrical stresses (e.g., ESD stress) across those regions and cause the parasitic bipolar transistors to break down in both the forward and reverse directions. For example, when a positive ESD stress as measured from the collector to the emitter is applied (e.g., from the isolation region 104 to the drain 108 for T1, from the isolation region 104 to the source 110 for T2, from the drain 108 to the source 110 for T3), the parasitic npn transistors T1, T2, and T3 may break down in the forward direction. In this kind of breakdown, an electron avalanche is created at a reverse biased collector base junction, a drifting of holes raises the backgate 106's potential, and the emitter diode becomes forward biased. This causes the bipolar transistor to enter a state referred to as “snapback” as it conducts the ESD current. For example, the ESD stress may be formed across the drain 108 (e.g., collector of T3) and the source 110 (e.g., emitter of T3). The junction of the drain 108 and the backgate 106 may become reverse biased, and an electron avalanche is created at this junction. A drifting of holes from the drain 108 towards the backgate 106 raises the potential of the backgate 106 and makes the backgate 106 to the source 110 diode become forward biased. Thus, T3 enters the snapback state and conducts the ESD current.
Protection circuits have been developed to protect IC chips from ESD. For example, an IC chip may be protected by a conventional NMOS transistor ESD protection circuit 200 as depicted in FIG. 2. The conventional NMOS transistor ESD protection circuit 200 may be termed as a “clamp cell” or “breakdown cell”. The conventional NMOS transistor ESD protection circuit comprises a single isolated NMOS transistor 100 with the gate 112 coupled to source 110 and backgate 106. As shown in FIG. 2, both of the source 110 and the backgate doped region 114 are connected to a terminal 2. The gate 112 is coupled to the terminal 2 via a resistor 220. The isolation region 104 is connected to a terminal 1 via a resistor 230 placed in series. The drain 108 is connected to a terminal 3. There is no resistor between the source 110 and the backgate doped region 114 and these two regions will maintain the same voltage at all times. During normal operations of the NMOS transistor, no electrical current flows between the terminal 2 and the gate 112, thus, the gate 112 and the source 110 will be kept at the same voltage level and the NMOS transistor will be off (e.g., an OFF-NMOS).
If static charges accumulate on either of the terminals, an ESD event may occur to discharge the static charges or neutralize them. During an ESD stress from the drain 108 to the source 110, in which the isolation region 104 (e.g., terminal 1) acts as an open circuit, this ESD protection circuit functions due to the breakdown of transistor T3. During the ESD event, the resistor 230 can limit the current that flows to the isolation region 104 because any electrical current flowing to terminal 1 will raise the potential level at the isolation region 104. Thus, the resistor 230 may reduce the potential difference between the drain 108 and the isolation region 104 and steer the ESD current away from the isolation region 104. Accordingly, even an ESD stress may take place across the drain 108 and the isolation terminal 1, the resistor 230 helps to prevent the damage that can occur if a large current flows from the drain 108 to the isolation terminal 1.
This OFF-NMOS ESD protection circuit be found between two power supply pins on an IC chip. For example, the terminal 3 may be connected to the high potential power supply VDD (e.g., positive (+) 12 volts) and the terminal 2 may be connected to the low potential power supply (e.g., negative (−) 12 volts). The terminal 1 may be connected to Viso, which may be grounded or a VSS (e.g., 3.3 volts).
One tool to analyze ESD effects on IC chips is transmission line pulse (TLP). TLP shows the quasistatic I/V characteristic of IC chips by applying electrical pulses with a variety voltage levels. Example TLP curves of the conventional NMOS ESD protection circuit 200 (e.g., an ESD clamp cell from a 24V CMOS process with isolated NMOS devices) are shown in FIG. 3, which includes an I/V curve 302 for ESD pulse and a curve 304 for leakage current after applying ESD pulses. Each point for the curve 302 may be obtained by applying a pulse (e.g., a fixed time period) with various voltage values. Each point of the curve 304 may be obtained by measuring a leakage current after applying each ESD pulse. Thus, for curve 302, the horizontal axis is the ESD voltage across the ESD clamp (e.g., between the source 108 and drain 110), the vertical axis is the ESD current through the ESD clamp. For curve 304, the horizontal axis is the leakage current under 2 Volts across the ESD clamp and the vertical axis represents the ESD pulse current.
The curve 302 has three different sections 302.1, 302.2 and 302.3. The curve 304 has two different sections 304.1 and 304.2. The TLP curve 302 indicates that this ESD clamp has a trigger voltage of about 35 volts. At a low ESD stress (between zero to 35 volts), the curve 302 indicates little or no ESD current flowing through the ESD clamp (e.g., little or no current flowing between the source 108 and the drain 110). And the section 302.1 coincides with the horizontal axis. When the stress voltage reaches an avalanche breakdown value (e.g., 35 volts), the ESD clamp breaks down and the ESD current begins to flow (e.g., the curve 302 enters the section 302.2). Once the ESD current begins, one of the parasitic bipolar transistor is turned on (e.g., the potential difference between the backgate 106 and the source 110 caused by the ESD current may turn on the parasitic bipolar transistor T3). The turning on of the bipolar transistor results in a drop in the ESD stress voltage (e.g., a snapback). During the section 302.2, the ESD current increases and the voltage across the ESD clamp continues to drop until it reaches to about 6˜7 volts. Then the ESD clamp has another turning point (e.g., entering the section 302.3). During the section 302.3, the ESD current increases but the ESD stress voltage changes very little.
The curve 304 indicates that when the ESD current is below a threshold (e.g., a failure current level), the leakage current does not change (e.g., section 304.1). Once the ESD current reaches the threshold (e.g., about 650 mA in FIG. 3), the leakage current value increases, which normally means the device is damaged (e.g., section 304.2). Thus, the this protection circuit only provides a ESD protection of up to 650 mA of ESD current. When the ESD current is larger than this threshold, the internal circuitry of the device will be damaged.
The conventional NMOS ESD protection circuit 200 has several shortcomings. For example, the trigger voltage as shown in FIG. 3 is relatively high for this process and there is a risk that internal circuitry may break down at a voltage lower than the trigger voltage of this ESD clamp. Further, because the voltage across the 2 terminals being stressed at the failure current level (about 7 Volts) is much lower than the trigger voltage of the cell, there is a likelihood that only one cell would break down during an ESD stress even if two or more clamp cells were placed in parallel. Because each clamp cell uses certain amount of layout area of an IC, thus, under this situation, although more layout areas of the IC chip are used, the failure current level would not increase but stay the same failure current level of one clamp cell. This is an undesirable characteristic for an ESD clamp cell.
Accordingly, there is a need in the art to design an ESD protection circuit (e.g., a clamp cell, or a breakdown cell) that has a lower trigger voltage than the internal circuitry that it is designed to protect, has a high breakdown failure current level for a given layout area, and the failure current should scale if a number of cells are placed in parallel.